1. Field of the Invention
The present invention relates to a logic circuit and a semiconductor integrated circuit including the logic circuit, and more particularly, to a circuit configuration and a method of controlling the circuit suitable for a power saving operation.
2. Description of Related Art
In recent years, a manufacturing process of a semiconductor integrated circuit has been miniaturized. Therefore, a withstand voltage of an MOS transistor forming the semiconductor integrated circuit such as a CMOS LSI has been decreasing and an operating voltage of the MOS transistor needs to be decreased. As the operating voltage decreases, operation speed of the MOS transistor is reduced. In order to prevent the operation speed from being reduced, a threshold voltage of the MOS transistor needs to be decreased.
However, when the threshold voltage is decreased (for example about 0.4 V or less), the transistor is not completely turned off, and a subthreshold leak current may flow between a drain and a source. This leak current causes a serious problem in the semiconductor integrated circuit such as an LSI formed by a plurality of MOS transistors. This is because a pass-through current is generated due to the leak current of the transistor even when the circuit in the semiconductor integrated circuit is logically in a disable state. There are caused significant problems due to the pass-through current such as increase of power consumption, increase of a load on a power source, decrease of energy consumption efficiency, and increase of heat release. Specifically, in the CMOS LSI performing high-speed operation, since the leak current increases in a speed exceeding the operating current due to the miniaturization of the transistor, the leak current needs to be reduced even in a slight time between operations.
A technique for reducing the leak current of the transistor requiring the high-speed operation and having a low threshold voltage is needed to realize both a circuit where the low-power operation is required and a circuit requiring the high-speed operation. Further, the above-mentioned problem can further be serious since the subthreshold leak current exponentially increases in high-temperature operation of the semiconductor integrated circuit. In order to overcome this problem, a technique for reducing the leak current in the circuit is necessary.
Various techniques for reducing the leak current have been suggested. One of such techniques is disclosed in Japanese Unexamined Patent Application Publication No. 2006-12968 (hereinafter referred to as related art). This related art relates to a configuration and a method of controlling a body voltage of a transistor for the purpose of reducing power consumption by reducing the leak current. In this related art, a source potential control circuit supplies source potential needed for an internal circuit block through a source potential line so as to control a current of a PMOS transistor.
However, we have now discovered that there is a problem in the above related art that the body voltage cannot finely be controlled in a short time. Further, there are problems that external environment such as temperature needs to be separately detected in performing the switching control, and that the variation such as a manufacturing process for each individual product has not been considered.